Wire management for coherence traffic in chip multiprocessors

Journal ArticleImprovements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future billion transistor architectures due to their low design complexity, high clock frequency, and high throughput. In a typical CMP architecture, the L2 cache is shared by multiple cores and data coherence is maintained among private L1s. Coherence operations entail frequent communication over global on-chip wires. In future technologies, communication between different L1s will have a significant impact on overall processor performance and power consumption. On-chip wires can be designed to have different latency, bandwidth, and energy properties. Likewise, coherence protocol messages have different latency and bandwidth needs. We propose an interconnect comprised of wires with varying latency, bandwidth, and energy characteristics, and advocate intelligently mapping coherence operations to the appropriate wires. In this paper, we present a comprehensive list of techniques that allow coherence protocols to exploit a heterogeneous interconnect and present preliminary data that indicates the potential of these techniques to significantly improve performance and reduce power consumption. We further demonstrate that most of these techniques can be implemented at a minimum complexity overhead

Interconnect-aware coherence protocols for chip multiprocessors

Journal ArticleImprovements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future billion transistor architectures due to their low design complexity, high clock frequency, and high throughput. In a typical CMP architecture, the L2 cache is shared by multiple cores and data coherence is maintained among private L1s. Coherence operations entail frequent communication over global on-chip wires. In future technologies, communication between different L1s will have a significant impact on overall processor performance and power consumption. On-chip wires can be designed to have different latency, bandwidth, and energy properties. Likewise, coherence protocol messages have different latency and bandwidth needs. We propose an interconnect composed of wires with varying latency, bandwidth, and energy characteristics, and advocate intelligently mapping coherence operations to the appropriate wires. In this paper, we present a comprehensive list of techniques that allow coherence protocols to exploit a heterogeneous interconnect and evaluate a subset of these techniques to show their performance and power-efficiency potential. Most of the proposed techniques can be implemented with a minimum complexity overhead

An O(1) time complexity software barrier

technical reportAs network latency rapidly approaches thousands of processor cycles and multiprocessors systems become larger and larger, the primary factor in determining a barrier algorithm?s performance is the number of serialized network latencies it requires. All existing barrier algorithms require at least O(log N) round trip message latencies to perform a single barrier operation on an N-node shared memory multiprocessor. In addition, existing barrier algorithms are not well tuned in terms of how they interact with modern shared memory systems, which leads to an excessive number of message exchanges to signal barrier completion. The contributions of this paper are threefold. First, we identify and quantitatively analyze the performance deficiencies of conventional barrier implementations when they are executed on real (non-idealized) hardware. Second, we propose a queue-based barrier algorithm that has effectively O(1)time complexity as measured in round trip message latencies. Third, by exploiting a hardware write-update (PUT) mechanism for signaling, we demonstrate how carefully matching the barrier implementation to the way that modern shared memory systems operate can improve performance dramatically. The resulting optimized algorithm only costs one round trip message latency to perform a barrier operation across N processors. Using a cycle-accurate execution-driven simulator of a future-generation SGI multiprocessor, we show that the proposed queue-based barrier outperforms conventional barrier implementations based on load-linked/storeconditional instructions by a factor of 5.43 (on 4 processors) to 93.96 (on 256 processors)

Certificateless Public Key Signature Schemes from Standard Algorithms

Certificateless public key cryptography (CL-PKC) is designed to have succinct public key management without using certificates at the same time avoid the key-escrow attribute in the identity-based cryptography. However, it appears difficult to construct CL-PKC schemes from standard algorithms. Security mechanisms employing self-certified key (also known as implicit certificate) can achieve same goals. But there still lacks rigorous security definitions for implicit-certificate-based mechanisms and such type of schemes were not analyzed formally and often found vulnerable to attacks later. In this work, we first unify the security notions of these two types of mechanisms within an extended CL-PKC formulation. We then present a general key-pair generation algorithm for CL-PKC schemes and use it with the key prefixing technique to construct certificateless public key signature (CL-PKS) schemes from standard algorithms. The security of the schemes is analyzed within the new model, and it shows that the applied technique helps defeat known-attacks against existing constructions. The resulting schemes could be quickly deployed based on the existing standard algorithm implementations. They are particularly useful in the Internet of Things (IoT) to provide security services such as entity authentication, data integrity and non-repudiation because of their low computation cost, bandwidth consumption and storage requirement

On Security Proof of McCullagh-Barreto\u27s Key Agreement Protocol and its Variants

McCullagh and Barreto presented an identity-based authenticated key agreement protocol in CT-RSA 2005. Their protocol was found to be vulnerable to a key-compromise impersonation attack. In order to recover the weakness, McCullagh and Barreto, and Xie proposed two variants of the protocol respectively. In each of these works, a security proof of the proposed protocol was presented. In this paper, we revisit these three security proofs and show that all the reductions in these proofs are invalid, because the property of indistinguishability between their simulation and the real world was not held. As a replacement, we slightly modify the McCullagh and Barreto\u27s second protocol and then formally analyse the security of the modified scheme in the Bellare-Rogaway key agreement model

Outcome of patients with stable angina pectoris treated with or without percutaneous coronary intervention

Background: To assess the outcome of patients with stable angina pectoris treated with percutaneous coronary intervention versus medically treated patients. Methods: Eighty patients with stable angina pectoris and coronary stenosis as confirmed in coronary angiography were treated with (n = 31) or without (n = 49) percutaneous coronary intervention in our department. All patients received optimal medical therapy and were followed up for a period of 24 months. Results: Baseline clinical characteristics, including risk factors of coronary heart disease and coronary lesion type did not differ between the two groups (all p > 0.05). There was no significant difference in major adverse cardiac events (22.4% vs. 22.6%) during the 24 month follow-up between the two groups (p > 0.05). Conclusions: Percutaneous coronary intervention did not provide extra benefit in this group of patients with stable angina pectoris receiving standard medical treatment in terms of 24 months major adverse outcomes. (Cardiol J 2008; 15: 226-229

Two-stage estimation of limited dependent variable models with errors-in-variables

Summary This paper deals with censored or truncated regression models where the explanatory variables are measured with additive errors. We propose a two-stage estimation procedure that combines the instrumental variable method and the minimum distance estimation. This approach produces consistent and asymptotically normally distributed estimators for model parameters. When the predictor and instrumental variables are normally distributed, we also propose a maximum likelihood based estimator and a two-stage moment estimator. Simulation studies show that all proposed estimators perform satisfactorily for relatively small samples and relatively high degree of censoring. In addition, the maximum likelihood based estimators are fairly robust against non-normal and /or heteroskedastic random errors in our simulations. The method can be generalized to panel data models

Radix Astragali-Based Chinese Herbal Medicine for Oxaliplatin-Induced Peripheral Neuropathy: A Systematic Review and Meta-Analysis

Background. Treatment of chemotherapy-induced peripheral neuropathy (CIPN) remains a big challenge for oncologists. The aim of this study is to evaluate the effects of Radix Astragali- (RA-) based Chinese herbal medicine in the prevention and treatment of oxaliplatin-induced peripheral neuropathy, including the incidence and grading of neurotoxicity, effective percentage, and nerve conduction velocity. Methods. All randomized controlled trials (RCTs) were found using PubMed, Cochrane, Springer, China National Knowledge Infrastructure (CNKI), and Wanfang Database of China Science Periodical Database (CSPD) by keyword search. Meta-analysis was conducted using RevMan 5.0. Results. A total of 1552 participants were included in 24 trials. Meta-analysis showed the incidence of all-grade neurotoxicity was significantly lower in experimental groups and high-grade neurotoxicity was also significantly less. Effective percentage was significantly higher and sensory nerve conduction velocity was improved significantly, but changes in motor nerve conduction velocity were not statistically significant. No adverse events associated with RA-based intervention were reported. Conclusion. RA-based intervention may be beneficial in relieving oxaliplatin-induced peripheral neuropathy. However, more double-blind, multicenter, large-scale RCTs are needed to support this theory. Trial Registration. PROSPERO International prospective register of systematic reviews has registration number  CRD42015019903

Type I interferons suppress viral replication but contribute to T cell depletion and dysfunction during chronic HIV-1 infection

The direct link between sustained type I interferon (IFN-I) signaling and HIV-1-induced immunopathogenesis during chronic infection remains unclear. Here we report studies using a monoclonal antibody to block IFN-α/β receptor 1 (IFNAR1) signaling during persistent HIV-1 infection in humanized mice (hu-mice). We discovered that, during chronic HIV-1 infection, IFNAR blockade increased viral replication, which was correlated with elevated T cell activation. Thus, IFN-Is suppress HIV-1 replication during the chronic phase but are not essential for HIV-1-induced aberrant immune activation. Surprisingly, IFNAR blockade rescued both total human T cell and HIV-specific T cell numbers despite elevated HIV-1 replication and immune activation. We showed that IFNAR blockade reduced HIV-1-induced apoptosis of CD4+ T cells. Importantly, IFNAR blockade also rescued the function of human T cells, including HIV-1-specific CD8+ and CD4+ T cells. We conclude that during persistent HIV-1 infection, IFN-Is suppress HIV-1 replication, but contribute to depletion and dysfunction of T cells